With innovative technologies, ASIC manufacturers are able to deliver system complexities up to 15-million gates on a single chip. Complete systems comprising cores, memories, and random logic are integrated on a single piece of silicon. Designers may design and verify a complete system for sign-off by submitting complex system models to electronic design automation (EDA) and verification and floor-planning tools to design and verify the complete system, including the core.
Automated memory compilers provide designers with the ability to generate their own application-specific memory models for single and multi-port memories. These models are expressed in native VHDL and Verilog formats as well as in formats that can be used by synthesis tools and static timing analysis tools.
Whenever memories are integrated into an ASIC, appropriate tests have to be conducted to make sure that the ASIC is not shipped to customers with faulty memories. The assignee of the present invention fabricates ASIC RAM's with a built-in self test (RAMBIST) as the mechanism to test RAM's (Logicvision is one vendor that provides software tools that allow designers to generate RAMBIST structures).
A memory compiler creates RAMBIST memory structures so that memories are fully testable. A RAMBIST test controller writes marching patterns into memory, reads them back out, and reports manufacturing defects. In production-test mode, the RAMBIST controllers output a simple pass-fail signal, which speeds test results analysis.
A major obstacle to quickly implementing RAMBIST structures in ASICs is the complexity of the RAMBIST generation flow. As a natural extension of the ASIC domain, RAMBISTs are designed using the same basic design flow traditionally employed for ASICs designers. Thus, designers have begun to use many of the same steps and checklists for ASIC memories as employed in ASIC development.
FIG. 1 is a block diagram illustrating a conventional ASIC design flow. The design flow includes a front-end design process that creates a logical design for the ASIC, and a back-end design process that creates a physical design for the ASIC. The front-end design process begins with providing a design entry 10 for an electronic circuit that is used to generate a high-level electronic circuit description, which is typically written in a Hardware Description Language (HDL) 12. Although many proprietary HDLs have been developed, Verilog and VHDL are the major standards.
The design includes a list of interconnections that need to be made between the cells of the circuit; but physical properties for the interconnects have yet to be determined. Therefore, the designer needs an estimation of physical properties to help determine timing within circuit. Interconnect data from previous designs are used to generate interconnect statistical data to use as the estimation in step 14. The interconnect statistical data is used to create a wire load model 16, which defines the resistance, capacitance, and the area of all nets in the design. The statistically generated wire load model 16 is used to estimate the wire lengths in the design and define how net delays are computed.
The HDL 12 and the wire load model 16 are then input into a logic synthesis tool 18 to generate a list of logic gates and their interconnections, called a “netlist” 20. It is important to use wire load models 16 when synthesizing a design, otherwise, timing information generated from synthesis will be optimistic in the absence of net delays. The timing information will also be inaccurate when a poor wire load model 16 is used.
Next, system partitioning is performed in step 22 in which the physical design is partitioned to define groupings of cells small enough to be timed accurately with wire load models 16 (local nets). The resulting design typically includes many cells with many interconnect paths. A prelayout simulation is then performed in step 24 with successive refinement to the design entry 10 and to logic synthesis 18 to determine if the design functions properly.
After prelayout simulation 24 is satisfactory, the back-end design process begins with floorplanning in step 26 in which the blocks of the netlist 20 are arranged on the chip. The location of the cells in the blocks are then determined during a placement process in step 28. A routing process makes connections between cells and blocks in step 30. Thereafter, circuit extraction determines the resistance and capacitance of the interconnects in step 32. A postlayout simulation is then performed in step 34 with successive refinement to floorplanning 26 as necessary.
A RAMBIST generation flow is similar, but currently encompasses approximately nineteen discrete steps and involves the use of both internal software programs developed by the ASIC vendor plus various third party tools.
Although the generation flow utilizes software tools, the flow is basically a manual one that is based on the experience of the designer, and which causes the designer to complete the design using trial and error. For example, throughout the design process, designers must invoke the correct software tool enter input into individual command lines. During floor-planning and placement, designers use their experience to arrange the initial placement of the cells, resulting in layouts that may not optimize density. In addition, the design flow is not perceived by the customers of ASIC manufacturers as adding value. Therefore, ASIC manufacturers must perform this complex, time-consuming service for free.
Accordingly, what is needed is an improved method for performing the instantiating BIST modules in ASIC memory designs. The present invention addresses such a need.